Software tools are frequently used in the design of analog, mixed-signal and custom digital circuits. In front-end design-for-yield, designers must choose device sizes such that the maximum possible percentage of manufactured chips meet all specifications such as, e.g., gain >60B and a power consumption <1 mW. As such, the designers strive to maximize the yield of electrical circuit designs.
The design-for-yield problem of an ECD can easily include thousands of variables because there may be any number of devices in the ECD, each device having features of adjustable sizes, and being subject to any number of process variables, which are random in nature. The space of possible designs is very high as well, because there may by any number of design variables (variable dimensions or sizes) per device. Environmental variables such as, e.g., temperature and load conditions must be considered as well. Many these effects can be simulated simultaneously in any suitable electronic circuit simulator such as, e.g., a Simulation Program with Integrated Circuit Emphasis (SPICE) software. However, the design problem is hard to decompose into simpler problems because the variables often have nonlinear interactions. All these variables impede a designer's ability to understand the issues affecting yield early in the design stage, and therefore his ability to choose device sizes that maximize yield.
One approach to handle the large number of interacting variables is to use an automated circuit-sizing tool. Unfortunately, the tool may not be able to simultaneously scale to a large number of process variables, environmental variables, and design variables, be accurate, and have reasonable runtime. Even if such automated sizing tools can handle those issues, the designers will often choose to not use them because, in the past, many sizers have been unreliable. Further, automated sizing tools tend to take away the designer's sense of control in the design. As will be appreciated, designers need to have a sense of control and trust in the design that they create because they, not the automated sizer, are ultimately responsible for the design's success upon fabrication. Manual iterations remain by far the most common approach to circuit sizing, and it will likely remain like this for years to come.
To overcome problems with respect a high number of variables, designers often try to prune down, or simplify, their design problem with respect to process variables and environmental variables. For example, instead of explicitly acknowledging possibly thousands of random process variables and environmental variables, effects are captured as global process corners. An example of such global process corners can be drawn from CMOS device models having their process variables set to model an NMOS component having possible fast or slow behaviors, and a PMOS component also having possible fast or slow behaviors. The CMOS device can then be analyzed at Fast(NMOS)/Fast(PMOS), Fast (NMOS)/Slow(NMOS), Slow(PMOS)/Fast(NMOS), and Slow(PMOS)/Slow(NMOS) global process corners. Another reason for using global process corners is that they are usually readily available from the chip foundry (fab), because such corners have traditionally nicely bracketed, for digital circuits, the key digital performance characteristics of speed and power.
Designers also typically handle environmental variables with corners. For example, in the case where temperature (T) and resistance (R) are environmental variables, global corners can be defined as (Low_T, Low_R), (Low_T, High_R), (High_T, Low_R) and (High_T, High_R). Accordingly, an overall corner has both settings for environmental and process variables. Therefore, instead of having to consider thousands of random and environmental variables during design, designers have reduced the design problem to that of sizing the circuit such that it meets the specifications at the pre-determined corners. Note that by using corners on process variables, they are also implying that they target 100% yield (or near-100% yield) rather than the best yield possible. This is acceptable since most practical industrial designs do expect near-100% yields for each sub-circuit of the design in order to proceed to fabrication.
Another practice that designers have is to get the ECD first working at a typical global process corner and at a typical environmental corner, and then, upon the ECD meeting the specifications at that corner, to add more corners. This has been a reasonable approach because the device sizes tend to have the biggest impact on circuit performance, followed by random and environmental effects. Automated circuit sizers can also have their problems simplified to global process corners combined with environmental corners, and indeed this is what has been done in practice for years.
An example of the above-noted circuit sizing method, which can also be referred to as a circuit sizing flow, or, simply a flow, can be written as:                1. corner=typical global process corner & typical environmental corner        2. change device sizes to meet specifications at corner, using SPICE for feedback (manual or automatic)        3. corners=cross-product of global process corners and a representative coverage of environmental space        4. change device sizes to meet specifications at corners, using SPICE for feedback (manual or automatic)        5. optionally manually choose more corners and add to corners, and go to step 4.As noted, steps 2 and 5 can be manual or automatic, depending on designer preference.        
The main problem with global process corners, and therefore the flow described above, is that global corners do not include device-level process variations, which can also be referred to as local variations. To have a better measure of yield, designers can run a Monte-Carlo analysis, which draws random points from a probability distribution that describes both local & global process variation. For each random point, representing a local and global process variation, one or many environmental corners are simulated for one or more circuit analyses (e.g., AC, DC, or transient electrical behaviors). From the simulation results, performance values can be derived for each process and environmental point, and, from those values, one can compute the feasibility of each random point, and finally the yield. FIG. 1 shows a scatter plot of actual simulation data (circles) from a gain-boosted operational amplifier designed using a 90 nm CMOS process. The parameters plotted are phase margin as a function of spurious-free dynamic range. FIG. 1 shows how global process corners (diamonds) are a poor approximation of variation effects, compared to Monte Carlo samples. The discrepancy is primarily due to local variation effects, which are not accounted for in global process corners. Although Monte Carlo analysis does account for local variations, it requires a long time to complete (typically hours to days). For this reason, it is impractical to use such analyses repeatedly within a manual or automatic sizing loop. Accordingly, it is typically performed late in the front-end design process, as a verification step.
It is clear from FIG. 1 that the global corners do not account for, or give a good representation of, how much the length of a given transistor may vary, or other parameters that affect its electrical behavior such as, e.g., oxide thickness, or substrate doping concentration. For modern circuit geometries having small features sizes (e.g., 90 nm), the local process variations will often dominate the global variation effects. One particularly important case is where devices requiring matched geometries to function correctly vary independently (often referred to as device mismatch). This can cause significant loss in yield because mismatch can be a limiting factor in circuit performance (this is almost always the case in analog circuits). Therefore, meeting specifications at just global process corners can mean little to the overall yield of the design.
Given that sizing an ECD using just global process corners is inaccurate, and Monte Carlo in the sizing loop is too slow, there exists an approach that partially reconciles the issues. To our knowledge, it is not a common design practice yet, and is not published explicitly, but it nonetheless is implicit in existing industrial ECD design tools, and is used by leading-edge designers. At its core, this approach uses Monte Carlo sampling combined with a naïve process-corner discovery approach. This flow (method) for front-end design using local and global process corners can be described as follows.                1. corners=initial corner composed of {nominal global process point and typical environmental point}        2. change device sizes to meet specifications at corners, using SPICE for feedback        3. do Monte Carlo sampling on new design        4. if stopping conditions are met (e.g., target yield is hit), stop        5. do naïve process-corner discovery: from Monte Carlo sample data, for each performance metric, add the process and environmental corner that causes the metric's worst-case performance to corners        6. go to step 2There can be varying degrees of automation in this flow. For example, everything but the actual Monte Carlo sampling can be fully manual. Alternatively, the whole flow can be fully automatic. Other options, such as step 2 being semi-automatic (semi-manual), and step 5 being automatic, are also possible.        
This flow (method) is an improvement on the past methods, because it handles both local and global variations, yet does not have the slowness of Monte Carlo sampling as part of the sizing loop itself (step 2). It has pruned the problem difficulty down by treating the process variables space and the environmental variables space as corners rather than having to reconcile the massive number of variables directly. The problem difficulty has also been reduced by simplifying the overall goal from “get best yield” (<100%) to “go for 100% yield”. In this problem, pruning has not compromised accuracy, unlike the simplification that just uses global process corners. The flow also supports manual, automation-aided, and fully automated flows depending on user preference. Unfortunately, this method has issues. First, the design space can remain very large, possibly having hundreds of design variables (large for transistor-level design). Such a large design space means that the device-sizing step (2) can be intractable, inefficient, or lead to a sub-optimal design (i.e., unsolved at given corners). Furthermore, the naïve process-corner discovery step is too simplistic, which causes great inefficiency. For example, in a typical analog circuit having 15 performance metrics, there would be 15 new corners added in each re-loop from step 6 to step 2. Accordingly, after just a couple re-loops, the sizing step (2) starts to get as slow as Monte Carlo sampling which as already been established as being too slow.
Therefore, designers have no efficient method for sizing a broad range of ECDs that is variation-aware, because even the state-of-the-art approach does not scale to ECDs of medium to large size, ECDs that have a larger number of design variables and/or performance metrics.
Further, many existing computer-aided design (CAD) tools are designed to handle problems that are specified in terms of corners only, not problems that include probability density function as part of the problem input (e.g., as a model of process variation). Typically, the corners for these CAD tools only include global process variables (input as global process corners), sometimes environmental variables, rarely local process variables, and very rarely all three. Yet as local variations becomes more of an issue with shrinking process geometries, it is becoming important for these CAD tools to account for these variations. Many of the existing CAD tools, such as, for examples, digital timing analysis tools, are deeply entrenched and established, with a lot of capital investment and designer training tied to them. Accounting for local process variation effects directly as a probability distribution (e.g., statistical timing analysis) can mean that the whole CAD tool set, and its related design flow needs to change. This is unpalatable because it is costly and requires training as well. A better intermediate approach would be to account for the local process variations (and environmental variables, if needed) in corners, which can be input into the existing tools, thereby keeping the existing CAD tool infrastructure and design flows and engineers' training investment. Then, the challenge is to have an efficient, effective means to find representative corners for the design that do indeed include all the variations.
Therefore, there is a need for ECD flows that provide improved efficiency in circuit sizing. There is also a need for a flow that makes use of existing CAD tools and that accounts for local process variations.